VITUS H50 2017-04-05T13:59:32+00:00


65 mm² collimated to 50 mm² X-ray Silicon Drift Detector for XRF – EDX – TXRF Applications

Unique Features

  • 12.5 µm Be-Window
  • High performance module
  • Largest area in ultra compact TO8 housing

(Guaranteed Values)

Table 1: Beyond the guaranteed minimum key parameters shown in the table above, typical energy resolution of a Premium Class VITUS H50 SDD is better than 128 eV. P/B is typically greater than 18,000.
First amplification stage ASIC JFET JFET
Energy resolution ≤ 129 eV ≤ 129 eV ≤ 139 eV
Peak to background > 15,000 > 15,000 > 6,000
Peak to tail > 2,000 > 2,000 > 1,000
Optimal peaking time at max. cooling 1 µs 8 µs 8 µs
Absorption depth 450 µm Si 450 µm Si 450 µm Si
Peak shift stability up to 100 kcps < 1 eV < 1 eV < 1 eV
Max. input countrate 2,000 kcps 500 kcps 500 kcps
Windows 12.5 µm Be 12.5 µm Be 12.5 µm Be
Cooling performance
at +30°C heat sink temperature
∆T > 75 K ∆T > 75 K ∆T > 75 K
On-chip collimator multilayer multilayer multilayer
Ordering codes V5C2T0-H50-ML9BEV 129 V5F2T0-H50-ML9BEV 129 V5F2T0-H50-ML9BEV 139



Figure 1: The spectrum has been acquired in KETEK’s standard end qualification test stand with an Fe-55 source using an XIA Mercury signal processing unit. The input count rate has been 10 kcps at a peaking time of 1 µs. The spectrum shows a very good energy resolution for Mn-Kα and an excellent peak-to-background ratio.

Energy Resolution

Figure 2: Energy resolution (Mn-Kα) values for peaking times from 0.1 µs through 8 µs showing good FWHM values even for higher operating temperatures. Depending on the application the best performance can be achieved by an appropriate selection of peaking time and set operating temperature.

KETEK VITUS H50 SDD Energy Resolution vs. Peaking Time for different Chip Temperatures

KETEK VITUS H50 SDD Energy Resolution vs. Input Count Rate for different Peaking Times

Figure 3: The VITUS H50 shows excellent energy resolution stability for different input count rates up to reasonable deadtimes at each peaking time. The data was measured at optimum cooling witKetek Vitus SDD H50 Energy Resolution vs. Input Count Rate for different Peaking Times an Fe-55 source using an XIA Mercury signal processing unit.


Figure 4: The achievable VITUS H50 throughput is mainly influenced by the applied signal processing electronics. The shown data has been allocated with an XIA Mercury digital pulse processor which yields in an excellent throughput performance.

KETEK VITUS H50 SDD Throughput for different Peaking Times

KETEK VITUS H50 SDD Control Range

Control Range

Figure 5: The VITUS H50 can be operated at high ambient temperatures. The control range is given by the blue shaded area. Up to 80°C heat sink temperature the SDD can be operated stable at -20°C chip temperature without secondary cooling stage.


SDD Voltages and Currents

Ring1 (R1) -20 V ± 5 V 10 µA typ.
RingX (RX) -130 V ± 20 V 10 µA typ.
Back -60 V ± 5 V < 1 nA
Peltier Element 3.6 V 700 mA max.

General parameters

Temperature Monitor NTC thermistor 10 kΩ @ 25 °C
Output signal ramped reset type

CUBE based SDDs

VI/O 3.3 V ± 0.1 V < 1 mA
Vs 2 V ± 0.1 V < 1 mA
Vsss -5 V ± 0.1 V < 1 mA
Output gain 1.6 mV/keV ± 20 %

FET based SDDs (Premium and Standard)

Drain 3 V ± 0.5 V 3 mA
Source 0 V
Bulk -5 V ± 3 V
Reset 1 V 1 µs
Feedback ramped output
Output gain 0.9 mV/keV ± 30 %


  • Pin wiring according to VITUS Operation Block Diagram
  • Detector operating voltages should be RC low-pass filtered and linearly regulated (KETEK electronics recommended)
  • KETEK reset type charge sensitive pre-amplifier with internal triggered reset pulses recommended
  • Short wiring length between detector and pre-amplifier recommended
  • Detector may only be operated with an appropriate heat sink

Block Diagram

Pin Assignment