DPP Block Diagram: The Block Diagram shows the principle of operation of the Digital Pulse Processor (DPP). The main clock frequency is 25MHz, using a 12-bit ADC at 40MSPS. It has both an analogue gain before digitizing and a digital gain right after the digital filtering, which consists of digital shaping a digital Baseline Restoration (BLR), a Peak Detection and a digital Pile-Up Rejector (PUR). Also the SDD operating parameters can be set and read by an additional ADC in combination with a SPI Interface. The DPP is FPGA based and uses USB 2.0 Interface.
AXAS-D Operation Block Diagram: The diagram shows the principle of operation of the AXAS-D. It consists of a Low voltage Power supply for 3.3 and 1.2V, a thermoelectric cooler controller for the SDD Peltier, a high voltage (-180VDC) power supply, a sensor parameters control and measurement unit, the preamplifier and the Digital Pulse Processor (DPP) itself. It provides an overvoltage and polarity reversal protection. Connectors are USB 2.0, a Lemo Coax Preamplifier Output and for the SDD.